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ATmega128
Figure 150. Virtual Flash Page Load Register
STROBES
State
TDI
machine
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
Virtual Flash Page
Read Register
The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically
transferred from the Flash data page byte by byte. The first eight cycles are used to transfer the
first byte to the internal Shift Register, and the bits that are shifted out during these 8 cycles
should be ignored. Following this initialization, data are shifted out starting with the LSB of the
first instruction in the page and ending with the MSB of the last instruction in the page. This pro-
vides an efficient way to read one full Flash page to verify programming.
Figure 151. Virtual Flash Page Read Register
STROBES
State
TDI
machine
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
Programming
All references below of type “1a”, “1b”, and so on, refer to Table 130 .
Algorithm
314
2467X–AVR–06/11
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